Intel Stratix 10 14-nm low power FPGA 1SG280LU3F50E3XG

Description

Intel Stratix 10
14-nm low power
FPGA
1SG280LU3F50E3XG
Shipped on board.
Intel’s 14 nm Intel® Stratix® 10 GX FPGAs and SX SoCs deliver 2X the core
performance and up to 70% lower power over previous generation high-performance
FPGAs.
Featuring several groundbreaking innovations, including the all new Intel Hyperflex™
core architecture, this device family enables you to meet the demand for everincreasing
bandwidth and processing performance in your most advanced applications,
while meeting your power budget.
With an embedded hard processor system (HPS) based on a quad-core 64 bit Arm*
Cortex*-A53, the Intel Stratix 10 SoC devices deliver power efficient, application-class
processing and allow designers to extend hardware virtualization into the FPGA fabric.
Intel Stratix 10 SoC devices demonstrate Intel's commitment to high-performance
SoCs and extend Intel's leadership in programmable devices featuring an Arm-based
processor system.
Important innovations in Intel Stratix 10 FPGAs and SoCs include:
• All new Intel Hyperflex core architecture delivering 2X the core performance
compared to previous generation high-performance FPGAs
• Intel 14 nm tri-gate (FinFET) technology
• Heterogeneous 3D System-in-Package (SiP) technology
• Core fabric with up to 10.2 million logic elements (LEs)
• Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver
tiles
• Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane
performance
• M20K (20 Kb) internal SRAM memory blocks
• Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops
(PLLs)
• Hard PCI Express® Gen3 x16 intellectual property (IP) blocks
• Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every
transceiver channel
• Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
• Hard fixed-point and IEEE 754 compliant hard floating-point variable precision
digital signal processing (DSP) blocks with up to 10 TFLOP compute performance
with a power efficiency of 80 GFLOP per Watt
• Quad-core 64 bit Arm Cortex-A53 embedded processor running up to 1.5 GHz in
SoC family variants
• Programmable clock tree synthesis for flexible, low power, low skew clock trees
Dedicated secure device manager (SDM) for:
— Enhanced device configuration and security
— AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and
authentication
— Multi-factor authentication
— Physically Unclonable Function (PUF) service and software programmable
device configuration capability
• Comprehensive set of advanced power saving features delivering up to 70% lower
power compared to previous generation high-performance FPGAs
• Non-destructive register state readback and writeback, to support ASIC
prototyping and other applications
With these capabilities, Intel Stratix 10 FPGAs and SoCs are ideally suited for the most
demanding applications in diverse markets such as:
• Compute and Storage—for custom servers, cloud computing and datacenter
acceleration
• Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet
processing and traffic management
• Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
• Broadcast—for high-end studio distribution, head end encoding/decoding, edge
quadrature amplitude modulation (QAM)
• Military—for radar, electronic warfare, and secure communications
• Medical—for diagnostic scanners and diagnostic imaging
• Test and Measurement—for protocol and application testers
• Wireless—for next-generation 5G networks
• ASIC Prototyping—for designs that require the largest FPGA fabric with the
highest I/O count
Common to all Intel Stratix 10 family variants is a high-performance fabric based on
the new Intel Hyperflex core architecture that includes additional Hyper-Registers
throughout the interconnect routing and at the inputs of all functional blocks. The core
fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module
(ALM) and a rich set of high performance building blocks including:
• M20K (20 Kb) embedded memory blocks
• Variable precision DSP blocks with hard IEEE 754 compliant floating-point units
• Fractional synthesis and integer PLLs
• Hard memory controllers and PHY for external memory interfaces
• General purpose IO cells
To clock these building blocks, Intel Stratix 10 devices use programmable clock tree
synthesis, which uses dedicated clock tree routing to synthesize only those branches
of the clock trees required for the application. All devices support in-system, finegrained
partial reconfiguration of the logic array, allowing logic to be added and
subtracted from the system while it is operating.
All family variants also contain high speed serial transceivers, containing both the
physical medium attachment (PMA) and the physical coding sublayer (PCS), which can
be used to implement a variety of industry standard and proprietary protocols. In
addition to the hard PCS, Intel Stratix 10 devices contain multiple instantiations of PCI
Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane
configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The
hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power,
and increase your productivity.